(1) Field of the Invention
The present invention relates to an initial program loading system in an information processing system containing a central processing unit and peripheral apparatuses connected to the central processing unit. The initial program loading system is provided for transferring program data from one of the peripheral apparatuses to the central processing unit, and loading the program data in the central processing unit.
(2) Description of the Related Art
Distributed information processing systems conventionally include a number of processor units. In many recent distributed information processing systems, each of the processor units has the same hardware construction, but the respective processor units operate differently in accordance with programs which are loaded in the respective processor units. The programs are loaded in respective processor units in different ways before the respective processor units start their operation. That is, generally a number of peripheral apparatuses are connected to each processor unit. A program is transferred to the processor unit from a different one of the peripheral apparatuses which holds program data, and the unit is prepared to transfer the program data to the central processing unit in the processor unit.
FIG. 1 shows a configuration of a plurality of processors in a digital exchange system. The digital exchange system of FIG. 1 is comprised of a management processor 1, a plurality of call processors 2.sub.1, 2.sub.2, 2.sub.3, . . . , and a plurality of line processors 3.sub.1, 3.sub.2, 3.sub.3, . . . .
The management processor 1 controls the whole operation of the digital exchange system including the plurality of call processors 2.sub.1, 2.sub.2, 2.sub.3, . . . , and the plurality of line processors 3.sub.1, 3.sub.2, 3.sub.3, . . . . Further, reference numeral 5 denotes a magnetic tape device, 9 denotes an operation console, CCA denotes a channel-to-channel adapter, CSC denotes a common signal controller, and SGC denotes a signal controller.
The channel-to-channel adapter CCA is equipped in the management processor 1 and each of the call processors 2.sub.1, 2.sub.2, 2.sub.3, . . . for interfacing between the management processor 1 and the call processors 2.sub.1, 2.sub.2, 2.sub.3. . . . The common signal controller CSC is equipped in each of the line processors 3.sub.1, 3.sub.2, 3.sub.3, . . . and the signal controller SGC is equipped in each of the line processors 3.sub.1, 3.sub.2, 3.sub.3, . . . for interfacing between the respective line processor 3.sub.1, 3.sub.2, 3.sub.3, . . . and the corresponding call processors 2.sub.1, 2.sub.2, 2.sub.3, . . . .
The call processors 2.sub.1, 2.sub.2, 2.sub.3, . . . each control a speech path memory (not shown), the line processors 3.sub.1, 3.sub.2, 3.sub.3, . . . each control a line circuit (not shown), and all the processors cooperate with each other to realize a consistent operation of the digital exchange system. Although each of the management processor 1, the call processors 2.sub.1, 2.sub.2, 2.sub.3, . . . , and the line processors 3.sub.1, 3.sub.2, 3.sub.3, . . . respectively realize different functions, all of these processors have the same hardware construction so that total production cost is reduced by enabling mass production. Different respective programs (operating systems) are initially loaded for the processors to realize the above different functions (initial program loading operation, IPL).
The initial program loading operation includes its initial stage of loading a boot program (bootstrap loader) which realizes a function of reading (and loading by itself) a total operating system. To load different operating systems in respective processors, different bootstrap loaders must be loaded in the respective processors. Although the above processors have the same construction, respective processors are generally located in different situations, and are generally connected to a plurality of peripheral apparatuses, e.g., a magnetic disc device, a magnetic tape device, terminal equipment, or the like. The initial program loading operation of the processors in the construction of FIG. 1 can be carried out by transferring program data of bootstrap loaders for the respective processors, for example, from the magnetic tape device 5 which is connected to the management processor 1. Further, generally each processor in the construction of FIG. 1 can connect thereto one or more I/O devices, and the bootstrap loader can be transferred to the processor from one of the I/O devices connected thereto. Namely, each processor has a plurality of suppliers of the bootstrap loader.
FIG. 2 is a schematic diagram of a processor unit which includes one of the above processors (for example, a line processor in the construction of FIG. 1) in the conventional distributed information processing system. In FIG. 2, reference numeral 11 denotes a central processor (CPU), 12 denotes a main memory, 13 denotes a channel controller, 14 denotes a channel-to-channel adapter, 15 denotes a magnetic disc device, 16 denotes a magnetic tape device, 17 denotes a main memory bus, and 18 denotes an input and output (I/O) bus.
The channel controller 13 is located between the main memory bus 17 and the I/O bus 18 for controlling operations of data transfer between the main memory 13 and the peripheral apparatus independently from the CPU 11. The channel-to-channel adapter 14 in the processor unit of FIG. 2 is to be connected to another channel-to-channel adapter in another apparatus to carry out data transfer between the processor unit of FIG. 2 and the other apparatus. Generally, the processor unit of FIG. 2 can receive program data from either of the channel-to-channel adapter 14, the magnetic disc device 15, the magnetic tape device 16, or the peripheral apparatus from which the processor unit should receive program data (bootstrap loader) in the initial program loading operation, which varies depending on various situations of the processor unit. Therefore, it is necessary to instruct the processor unit from which peripheral apparatus the processor unit should receive program data (bootstrap loader) in the initial program loading operation.
Conventionally, each processor unit in a distributed information processing system comprises a unit to receive a manual input for instructing the processor unit from which peripheral apparatus the program data should be received, for example, a DIP switch. When an IPL switch (not shown) is turned ON, an IPL request signal is generated and is input into the central processor 11. The central processor 11 comprises a ROM (not shown), and memorizes a microprogram for the initial program loading operation, in the ROM. Responding to the above IPL request signal, and in accordance with the microprogram, the central processor 11 reads the above input from the DIP switch, and the operation jumps to a vector address in the microprogram which corresponds to that input. In accordance with instructions in the microprogram beginning at the vector address, the central processor 11 carries out an initial program loading operation to receive a bootstrap loader from a peripheral apparatus which is instructed by the above manual input in the DIP switch.
However, according to the above conventional method to input an instruction to select a peripheral apparatus which supplies the bootstrap loader, to each processor unit individually and manually, an error is liable to occur when inputting the manual instruction to each processor unit. Further, when a new processor unit is added to the distributed information processing system, or when modifying processor configuration in the distributed information processing system, the above-mentioned microprogram which is memorized in the ROM in each processor unit, must be renewed or modified. Therefore, the above conventional method heavily reduces the flexibility in modifying a processor configuration in a distributed information processing system.